BH2226FV-FE2【PDF 11/12 页】IC DAC 8BIT 8-CHAN SSOP-B16

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Sheet目录1990

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BH2226FV,BH2226F

Technical Note

8/9

www.rohm.com

2009.07 - Rev.B

●Operation Notes

(1) Numbers and data in entries are representative design values and are not guaranteed values of the items.

(2) Although we are confident in recommending the sample application circuits, carefully check their characteristics further

when using them.

When modifying externally attached component constants before use, determine them so that they

have sufficient margins by taking into account variations in externally attached components and the Rohm LSI, not only

for static characteristics but also including transient characteristics.

(3) Absolute Maximum Ratings

Operating or testing the device over the maximum specifications may damage the part itself as well as peripheral

components. Therefore, please ensure that the specifications are not exceeded.

(4) GND potential

Ensure that the GND terminal is at the lowest potential under all operating conditions.

(5) Thermal design

Use a thermal design that allows for a sufficient margin regarding power dissipation (Pd) under actual operating conditions.

(6) Terminal shorts and mis-mounting

Incorrect orientation or misalignment of the IC when mounting to the PCB may damage part. Short-circuits caused by

the introduction of foreign matter between the output terminals or across the output and power supply or GND may also

result in destruction.

(7) Operation in a strong magnetic field

Operation in a strong electromagnetic field may cause malfunction.

(8) Reset Function

The power on reset circuit, which initializes internal settings, may malfunction during abrupt power ons. Therefore, set

the time constant so as to satisfy the power source rise time.

(9) After power on and after the external reset is in power down status, DA1 ~ DA8 will be in input mode (all terminals at

High-Z).

(10) In the case of condition changes in the DA1 ~ DA8 terminals (i.e. changes from D/A mode to serial-parallel mode, from

serial-parallel mode to parallel-serial mode, excluding D/A data and I/O data updates), change both analog and digital

settings of High-Z.

(11) Connect the RESETB terminal to VCC and set it to High, making sure that it becomes Low only at reset.

(12) Initialization of the serial interface shift register is carried out only by power on reset, or external reset, and is not reset

by CSB = High. Therefore, when a specified clock number (12CLK) is not attained during command setting,

interrupting processing, transfer regular data once again.

(13) The power down function restricts the consumption current in the internal analog circuit. Set it by command. At power

down, for channels set to D/A mode, "I/O D/A selection" is changed from "D/A mode" to "I/O mode". Therefore, when

the "I/O status setting" of the channel is in input mode, the terminal is in High-Z status and the input becomes unstable

and unnecessary current flows. Set the I/O status setting of channel to be in output mode, or set the terminal using

resistance.

(14) When shifting from PIO use status to D/A use status, a wait time in order to ensure D/A output stability is necessary.

Therefore wait for a maximum of 1ms after the "I/O D/A select" command is input.

If wait time is problematic, set the D/A setting code to 80hex and change it to the specified code setting.

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